1. Technical Field
Embodiments described herein relate generally to a semiconductor memory apparatus, and more particularly, to a data alignment circuit of a semiconductor memory apparatus.
2. Related Art
A conventional semiconductor memory apparatus transmits and receives plural bits of data to and from an external memory control apparatus in series. Further, the internal components of a semiconductor memory apparatus include a plurality of global data buses (GIOs) for transmitting or outputting the plural bits of data to or from a core area. The plural bits of data are transmitted in parallel through the global data buses. As such, the plural bits of data are transmitted in parallel when inside the semiconductor memory apparatus but are transmitted in series when outside the semiconductor memory apparatus. The differing internal and external transmission methods require a data input area with a circuit for aligning serial data in parallel and a data output area with a circuit for aligning parallel data in series. For this, the semiconductor memory apparatus includes a data alignment circuit in each of the data input area and the data output area.
The data alignment circuit of the semiconductor memory apparatus generates a plurality of control signals in response to the input of plural bits of an address. The data alignment circuit modifies the order of alignment of received data in accordance with timings at which the control signals are enabled. To this end, the data alignment circuit of the semiconductor memory apparatus includes a control signal generator and a data alignment unit. The control signal generator performs an operation of generating the plurality of control signals from the plural bits of the address.
FIG. 1 is a schematic configuration diagram of a control signal generator 100 of the data alignment circuit of a semiconductor memory apparatus.
Referring to FIG. 1, the control signal generator 100 of the data alignment circuit of the semiconductor memory apparatus includes two flip-flops FFA and FFB that operate by a clock signal ‘CLK’ and a combinational logic circuit 1 therebetween that generates a control signal ‘CTRL’ derived from an address ADD.
The desire to achieve the highest possible operation speed of a semiconductor memory apparatus has in turn led to an increase in the frequency of the clock signal ‘CLK’. Referring to the configuration of the control signal generator 100 shown in FIG. 1, since the combinational logic circuit 1 is disposed between the two flip-flops FFA and FFB, the combination logic circuit 1 should complete operations within a prescribed time. However, the clock signal's ‘CLK’ high frequency restricts the operable time of the combinational logic circuit 1. Although a detailed internal configuration is not shown, the combinational logic circuit 1 is generally configured in a manner in which a signal path advances through 7 to 11 transistors. This signal path imposes a limit on improvement of the operation speed of the combinational logic circuit 1. Consequently, it is difficult for the control signal generator 100 to perform high-speed operation.
According, high-speed operation of a semiconductor memory apparatus requires both internal components suitable for implementing high-speed operation and a data alignment circuit configured to operate using a high-frequency clock signal. However, as described above, the configuration of a typical data alignment circuit limits the ability to shorten the operation time required to generate the control signal making it difficult for the data alignment circuit to appropriately implement high-speed operation. Consequently, the data alignment circuit of the semiconductor memory apparatus that can implement the high-speed operation should be implemented by performing a normal operation when the high-frequency clock signal is inputted.